PCI: Disable Relaxed Ordering Attributes for AMD A1100
Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe
Root Port where Upstream Transaction Layer Packets with the Relaxed
Ordering Attribute clear are allowed to bypass earlier TLPs with
Relaxed Ordering set, it would cause Data Corruption, so we need
to disable Relaxed Ordering Attribute when Upstream TLPs to the
Root Port.
Reported-and-suggested-by: Casey Leedom <leedom at chelsio.com>
Signed-off-by: Casey Leedom <leedom at chelsio.com>
Signed-off-by: Ding Tianhong <dingtianhong at huawei.com>
Acked-by: Casey Leedom <leedom at chelsio.com>
Signed-off-by: David S. Miller <davem at davemloft.net>
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