LLVM/llvm 366124libcxx/trunk/include unordered_map, libcxx/trunk/test/std/containers/unord/unord.map/unord.map.cnstr deduct.pass.cpp deduct_const.pass.cpp

[libc++] Implement P0433: deduction guides for <unordered_map>

Thanks to Arthur O'Dwyer for the patch.

Differential Revision: https://reviews.llvm.org/D58590

LLVM/llvm 366123cfe/trunk/lib/CodeGen SanitizerMetadata.cpp, cfe/trunk/lib/Driver SanitizerArgs.cpp

ARM MTE stack sanitizer.

Add "memtag" sanitizer that detects and mitigates stack memory issues
using armv8.5 Memory Tagging Extension.

It is similar in principle to HWASan, which is a software implementation
of the same idea, but there are enough differencies to warrant a new
sanitizer type IMHO. It is also expected to have very different
performance properties.

The new sanitizer does not have a runtime library (it may grow one
later, along with a "debugging" mode). Similar to SafeStack and
StackProtector, the instrumentation pass (in a follow up change) will be
inserted in all cases, but will only affect functions marked with the
new sanitize_memtag attribute.

Reviewers: pcc, hctim, vitalybuka, ostannard

Subscribers: srhines, mehdi_amini, javed.absar, kristof.beyls, hiraditya, cryptoad, 
steven_wu, dexonsmith, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D64169

LLVM/llvm 366122libcxx/trunk CMakeLists.txt

Constrain workaround to avoid affecting other buildbots

LLVM/llvm 366121llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp AMDGPUInstructionSelector.h, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel inst-select-or.mir inst-select-xor.mir

AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR

LLVM/llvm 366120llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel inst-select-copy.mir

AMDGPU/GlobalISel: Don't constrain source register of VCC copies

This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.

This is necessary to successfully select branches with and and/or/xor
condition.

LLVM/llvm 366119llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel inst-select-copy.mir

AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies

The extra test change is correct, although how it arrives there is a
bug that needs work. With wave32, the test for isVCC ambiguously
reports true for an SCC or VCC source. A new allocatable pseudo
register class for SCC may be necesssary.

LLVM/llvm 366118llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel inst-select-copy.mir

AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC

LLVM/llvm 366117llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel inst-select-copy.mir

AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC

This was emitting a copy from a 32-bit register to a 64-bit.

LLVM/llvm 366116llvm/trunk/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp AMDGPULegalizerInfo.h, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel legalize-insert-vector-elt.mir

AMDGPU/GlobalISel: Custom legalize G_INSERT_VECTOR_ELT

LLVM/llvm 366115llvm/trunk/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp AMDGPULegalizerInfo.h, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel legalize-extract-vector-elt.mir

AMDGPU/GlobalISel: Custom legalize G_EXTRACT_VECTOR_ELT

Turn the constant cases into G_EXTRACTs.

LLVM/llvm 366114llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel inst-select-icmp.mir

AMDGPU/GlobalISel: Fix G_ICMP for wave32

LLVM/llvm 366113llvm/trunk/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel legalize-insert-vector-elt.mir legalize-extract-vector-elt.mir

GlobalISel: Implement narrowScalar for vector extract/insert indexes

LLVM/llvm 366112zorg/trunk/buildbot/osuosl/master/config status.py

Added MailNotifier for builders "llvm-clang-x86_64-win-fast" and "lld-x86_64-ubuntu-fast".

LLVM/llvm 366111zorg/trunk/buildbot/osuosl/master/config status.py

Removed MailNotifiers for removed builders.

LLVM/llvm 366110llvm/trunk/include/llvm/IR IntrinsicsAMDGPU.td, llvm/trunk/test/Verifier/AMDGPU intrinsic-immarg.ll

AMDGPU: Fix missing immarg from interp intrinsics

LLVM/llvm 366109llvm/trunk/include/llvm/Support FileCheck.h, llvm/trunk/lib/Support FileCheck.cpp

[FileCheck] Store line numbers as optional values

Summary:
Processing of command-line definition of variable and logic around
implicit not directives both reuse parsing code that expects a line
number to be defined. So far, a special line number of 0 was used for
those users of the parsing code where a line number does not make sense.
This commit instead represents line numbers as Optional values so that
they can be None for those cases.

Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk

Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, 
dblaikie, probinson, llvm-commits, hiraditya

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64639

LLVM/llvm 366108llvm/trunk/cmake/modules TableGen.cmake

[cmake] Don't set install rules for tblgen if building utils is disabled

Summary:
This is a follow up to D64032. Afterwards if building utils is disabled
and cross compilation is attempted, CMake will complain that adding
`install()` directives to targets with EXCLUDE_FROM_ALL set is "undefined".
Indeed, it appears depending on the CMake version and the selected
Generator, the install rule will error because the underlying target isn't
built. Fix that by not adding the install rule if building utils is not
requested. Note that this doesn't prevent building tblgen as a
dependency in not cross-build, even if building tools is disabled.

Reviewed By: smeenai
Differential Revision: https://reviews.llvm.org/D64225

LLVM/llvm 366107llvm/trunk/lib/DebugInfo/PDB/Native PDBStringTableBuilder.cpp

Expand comment about how StringsToBuckets was computed, and add more entries

The construction was explained in
https://reviews.llvm.org/D44810?id=139526#inline-391999 but reading the code
shouldn't require hunting down old reviews to understand it.

The precomputed list was missing an entry for the empty list case, and
one entry at the very end. (The current last entry is the last one where
3 * BucketCount fits in a signed int, but the reference implementation
uses unsigneds as far as I can tell, so there's room for one more entry.)

No behavior change for inputs seen in practice.

Differential Revision: https://reviews.llvm.org/D64738

LLVM/llvm 366106llvm/trunk/test/CodeGen/Thumb2 mve-fmath.ll mve-minmax.ll

[ARM] MVE vector for 64bit types

We need to make sure that we are sensibly dealing with vectors of types v2i64
and v2f64, even if most of the time we cannot generate native operations for
them. This mostly adds a lot of testing, plus fixes up a couple of the issues
found. And, or and xor can be legal for v2i64, and shifts combining needs a
slight fixup.

Differential Revision: https://reviews.llvm.org/D64316

LLVM/llvm 366105compiler-rt/trunk/lib/asan asan_malloc_win.cc

[sanitizers][windows][mingw32] Mingw32 RTL fixes
RTL interception broke mingw32, this should fix those builds by
removing dependency on windows.h

reviewed in https://reviews.llvm.org/D64694

LLVM/llvm 366104llvm/trunk/lib/MC/MCParser WasmAsmParser.cpp, llvm/trunk/test/MC/WebAssembly basic-assembly.s

[WebAssembly] Assembler: recognize .init_array as data section.

Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64602

LLVM/llvm 366103llvm/trunk/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel legalize-extract-vector-elt.mir

AMDGPU/GlobalISel: Widen vector extracts

LLVM/llvm 366102llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp AMDGPURegisterBankInfo.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.if.break.i32.ll llvm.amdgcn.if.break.i64.ll

AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break

LLVM/llvm 366101llvm/trunk/include/llvm/BinaryFormat ELF.h

AMDGPU: Remove reserved value accidentally left in for gfx908

LLVM/llvm 366100zorg/trunk/zorg/jenkins/jobs/jobs lldb-cmake-standalone

[lldb-cmake-standalone] Pre-populate provided LLVM build-tree cache with Apple-lldb-base

LLVM/llvm 366099llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp AMDGPURegisterBankInfo.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.end.cf.i32.ll llvm.amdgcn.end.cf.i64.ll

AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf

LLVM/llvm 366098llvm/trunk/lib/Target/X86 X86ISelLowering.cpp, llvm/trunk/test/CodeGen/X86 known-signbits-vector.ll known-bits-vector.ll

[x86] try to keep FP casted+truncated+extracted vector element out of GPRs

inttofp (trunc (extelt X, 0)) --> inttofp (extelt (bitcast X), 0)

We have pseudo-vectorization of scalar int to FP casts, so this tries to
make that more likely by replacing a truncate with a bitcast. I didn't see
any test diffs starting from 'uitofp', so I left that as a TODO. We can't
only match the shorter trunc+extract pattern because there's an opposing
transform somewhere, so we infinite loop. Waiting to try this during
lowering is another possibility.

A motivating case is shown in PR39975 and included in the test diffs here:
https://bugs.llvm.org/show_bug.cgi?id=39975

Differential Revision: https://reviews.llvm.org/D64710

LLVM/llvm 366097llvm/trunk/lib/ToolDrivers/llvm-lib CMakeLists.txt

[llvm-lib] Add a dependency to intrinsics_gen to the LLVMLibDriver build

Summary:
Occasionally the build of LLVMLibDriver will fail because Attributes.inc has not been 
generated yet. Add an explicit dependency, so that we can guarantee that the file has been 
generated before LLVMLibDriver is build.

##[error]llvm\include\llvm\IR\Attributes.h(73,0): Error C1083: Cannot open include file: 
'llvm/IR/Attributes.inc': No such file or directory
llvm\include\llvm/IR/Attributes.h(73): fatal error C1083: Cannot open include file: 
'llvm/IR/Attributes.inc': No such file or directory [LLVMLibDriver.vcxproj]

Reviewers: asmith

Subscribers: mgorny, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64357

LLVM/llvm 366096llvm/trunk/lib/Target/X86 X86ISelLowering.cpp

[X86] Return UNDEF from LowerScalarImmediateShift when the shift amount is out of range.

I think we only turn out of range shiftss to undef when
all elements are out of range or the shift amount is a splat out
of range. I'm not sure which, I didn't check.

During lowering we can split a shift where some elements
are out of range into multiple shifts. This can create a
new shift with a splat shift amount that is out of range.

This patch returns undef for this case.

Fixes PR42615.

Differential Revision: https://reviews.llvm.org/D64699

LLVM/llvm 366095lld/trunk/COFF SymbolTable.cpp, lld/trunk/test/COFF undefined-symbol-lto.test

Reland "[COFF] Add null check in case of symbols defined in LTO blobs"

This reverts r365990 (git commit 1a6053ebc61cb0b8146f5ca27b74859a9a91e0a3)

The test no longer depends on the Visual C++ libraries. I confirmed that
the crash still reproduces with the new test case if I remove the null
check.

LLVM/llvm 366094llvm/trunk/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/trunk/test/CodeGen/AMDGPU amdgpu-codegenprepare-mul24.ll mad_uint24.ll

AMDGPU: Add 24-bit mul intrinsics

Insert these during codegenprepare.

This works around a DAG issue where generic combines eliminate the and
asserting the high bits are zero, which then exposes an unknown read
source to the mul combine. It doesn't worth the hassle of trying to
insert an AssertZext or something to try to deal with it.

LLVM/llvm 366093llvm/trunk/docs ReleaseNotes.rst

Add some release notes for 9.0 release

LLVM/llvm 366092llvm/trunk/lib/Target/AMDGPU DSInstructions.td

[AMDGPU] Copy missing predicate from pseudo to real

NFC at the momemnt, needed for future commit.

Differential Revision: https://reviews.llvm.org/D64761

LLVM/llvm 366091cfe/trunk/docs ReleaseNotes.rst LanguageExtensions.rst, cfe/trunk/lib/Frontend InitPreprocessor.cpp

Update __VERSION__ to remove the hardcoded 4.2.1 version

Summary:
Just like in https://reviews.llvm.org/D56803
for -dumpversion

Reviewers: rnk

Reviewed By: rnk

Subscribers: dexonsmith, lebedev.ri, hubert.reinterpretcast, xbolva00, fedor.sergeev, 
cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D63048

LLVM/llvm 366090llvm/trunk/lib/Transforms/IPO FunctionAttrs.cpp, llvm/trunk/test/Transforms/FunctionAttrs read-write-scc.ll

[FunctionAttrs] Remove readonly and writeonly assertion

There are scenarios where mutually recursive functions may cause the SCC
to contain both read only and write only functions. This removes an
assertion when adding read attributes which caused a crash with a the
provided test case, and instead just doesn't add the attributes.

Patch by Luke Lau <luke.lau at intel.com>

Differential Revision: https://reviews.llvm.org/D60761

LLVM/llvm 366089llvm/trunk/lib/Target/ARM ARMInstrMVE.td

[ARM] Minor formatting in ARMInstrMVE.td. NFC

LLVM/llvm 366088cfe/trunk/include/clang/Basic SourceManager.h, cfe/trunk/lib/Basic SourceManager.cpp

Use a unique_ptr instead of manual memory management for LineTable

LLVM/llvm 366087llvm/trunk/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel inst-select-build-vector.mir

AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR

LLVM/llvm 366086llvm/trunk/lib/Target/AMDGPU AMDGPURegisterBankInfo.cpp, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel regbankselect-concat-vector.mir

AMDGPU/GlobalISel: RegBankSelect for G_CONCAT_VECTORS

LLVM/llvm 366085cfe/trunk/include/clang/Basic DiagnosticIDs.h, cfe/trunk/lib/Basic DiagnosticIDs.cpp

Use a unique_ptr instead of manual memory management for CustomDiagInfo

LLVM/llvm 366084cfe/trunk/lib/Driver Compilation.cpp

Use unique_ptr instead of manual delete in one place. No behavior change.

LLVM/llvm 366083lldb/trunk/source/Commands OptionsBase.td

[lldb][doc] Document how our LLDB table gen initialized options

Summary: This patch adds documentation that should make it easier to migrate from using 
the old initializers to the table gen format.

Reviewers: jingham

Reviewed By: jingham

Subscribers: abidh, lldb-commits, JDevlieghere

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D64670

LLVM/llvm 366082llvm/trunk/test/CodeGen/X86 phaddsub-extract.ll haddsub.ll

[x86] add tests for reductions that might be better with more horizontal ops; NFC

LLVM/llvm 366081llvm/trunk/include/llvm/IR PatternMatch.h, llvm/trunk/unittests/IR PatternMatch.cpp

Revert "r366069: [PatternMatch] Implement matching code for LibFunc"

Reason: the change introduced a layering violation by adding a
dependency on IR to Analysis.

LLVM/llvm 366080llvm/trunk/docs/CommandGuide llvm-nm.rst

[docs][llvm-nm] Fix inconsistent grammar

LLVM/llvm 366079llvm/trunk/test/CodeGen/X86 packss.ll

[X86][SSE] Regenerated packss.ll test file.

Not sure what went wrong in rL366077....

LLVM/llvm 366078zorg/trunk/buildbot/osuosl/master/config builders.py, zorg/trunk/zorg/buildbot/builders LLDBBuilder.py

[LLDB] getLLDBCMakeBuildFactory: New parameter testTimeout

It also uses the new long timeout for slave 'lldb-x86_64-fedora'.

Differential Revision: https://reviews.llvm.org/D64719

LLVM/llvm 366077llvm/trunk/test/CodeGen/X86 packss.ll

[X86][SSE] Add PACKSS with zero shuffle masks.

This is an example of expansion due to D61129 - it should combine back to a PACKSS with a 
zero operand.

LLVM/llvm 366076cfe/trunk/lib/CodeGen CGExpr.cpp CodeGenFunction.h, cfe/trunk/test/CodeGen builtin-preserve-access-index.c

fix unnamed fiefield issue and add tests for __builtin_preserve_access_index intrinsic

This is a followup patch for https://reviews.llvm.org/D61809.
Handle unnamed bitfield properly and add more test cases.

Fixed the unnamed bitfield issue. The unnamed bitfield is ignored
by debug info, so we need to ignore such a struct/union member
when we try to get the member index in the debug info.

D61809 contains two test cases but not enough as it does
not checking generated IRs in the fine grain level, and also
it does not have semantics checking tests.
This patch added unit tests for both code gen and semantics checking for
the new intrinsic.

Signed-off-by: Yonghong Song <yhs at fb.com>

LLVM/llvm 366075llvm/trunk/docs ORCv2.rst ORCv2DesignAndImplementation.rst

[ORC] Start adding ORCv1 to ORCv2 transition tips to the ORCv2 doc.